High-density interconnect technology has become the foundation of modern electronics, enabling compact wearables, advanced driver-assistance systems, medical implants, and high-speed telecom equipment. Designing an HDI board requires a different mindset than conventional PCB design because the mechanical, electrical, and manufacturing constraints are tightly interwoven. One of the most important decisions is how you implement microvias, since they directly affect routing density, signal integrity, thermal performance, and long-term reliability. If you are starting a new high-density layout, understanding How to Design HDI Microvia PCB requires careful planning of stackup, material behavior, laser drilling limits, and assembly requirements from the very first schematic review.
Defining Microvia Structures and HDI Design Rules
A microvia is generally defined as a laser-drilled via with a diameter of 0.15 mm or less and a dielectric thickness that typically does not exceed 0.1 mm. The defining characteristic of a microvia is its small aspect ratio, usually 1:1 or less, which allows precise laser formation and reliable copper plating. Unlike mechanically drilled through-holes, microvias can be placed directly in component pads, enabling via-in-pad designs that reduce inductance and free up routing space beneath fine-pitch BGAs. However, this benefit comes with strict design rules. The capture pad must be large enough to tolerate laser registration and material movement, but small enough to prevent solder wicking in via-in-pad applications. Typically, a microvia pad size is calculated as the laser drill diameter plus 0.1 mm to 0.15 mm, depending on the fabricator’s registration capability and the copper thickness.
HDI structures are commonly classified by levels such as 1+N+1, 2+N+2, or any-layer construction. A 1+N+1 stackup has one microvia layer on each side of a conventional core, while 2+N+2 adds a second microvia layer. Any-layer HDI, also called every-layer interconnect, uses microvias from every layer to every adjacent layer, which is essential for extremely dense designs with high pin-count processors. When designing these structures, you must decide between stacked and staggered microvia patterns. Stacked microvias align directly above or below each other, creating a vertical connection path through multiple layers. They save space but require precise laser alignment, copper filling, and flat plating. Staggered microvias offset each subsequent via, which is easier to manufacture but consumes more routing area.
Electrical and mechanical reliability rules also define how close microvias can be placed to each other and to the board edge. The annular ring around a microvia should not be reduced excessively, because the thin copper at the via rim is vulnerable to thermal cycling and mechanical stress. Designers should also avoid placing microvias in high-strain regions near board corners, mounting holes, or connector edges. In automotive and aerospace applications, thermal shock testing often reveals weaknesses in microvia plating when the dielectric thickness is pushed beyond the laser’s stable ablation range. A robust design keeps the dielectric below 0.08 mm for a 0.1 mm laser via, allowing the plating bath to fully wet the hole wall and form a uniform copper barrel. This balance between miniaturization and manufacturability is the foundation of successful HDI design.
Material Selection and HDI Stackup Planning
HDI stackup planning starts with dielectric material selection. The materials used in microvia layers must support laser drilling, maintain dimensional stability during sequential lamination, and provide the electrical performance required by high-speed signals. Common choices include resin-coated copper foil, also known as RCC, and thin glass-reinforced prepregs with low-profile copper. Laser-friendly materials have uniform glass distribution or no glass at all, because glass fibers can scatter laser energy and create rough or inconsistent via walls. A material with a low dielectric constant and low dissipation factor is preferred for high-frequency designs, but it must also have a high glass transition temperature and low coefficient of thermal expansion to survive multiple lamination cycles.
The stackup must remain symmetrical in copper weight, dielectric thickness, and material type to prevent warpage during lamination. Asymmetrical constructions can cause board twist, registration issues, and uneven microvia depths. For a typical 1+N+1 structure, the designer may use a central FR-4 or high-Tg core with symmetrical prepreg and RCC layers on each side. The laser then forms microvias through the outer RCC layer to the first internal copper plane. In a 2+N+2 structure, a second dielectric layer is laminated over the first microvia layer, and another set of microvias is laser-drilled and plated. Each sequential lamination cycle adds cost, time, and thermal stress to the board, so the layer count and HDI level should be optimized rather than over-specified.
For any-layer HDI boards, the entire stackup is built sequentially without a traditional rigid core. Every layer pair is connected by microvias, and the board becomes a true high-density interconnect structure. This approach is often used in flagship smartphones and advanced military systems where board thickness and routing density are extreme. However, any-layer construction requires very thin dielectrics, precision laser drilling, and multiple plating cycles. The designer must verify that the fabricator can control copper plating thickness across many lamination steps without closing off small via openings or creating dimples in filled vias. Thermal modeling is also essential because thin dielectrics reduce the board’s ability to spread heat away from power components.
A good stackup plan also defines copper thickness on each layer. Outer layers may use 0.5 oz copper to improve fine-line etching and laser drilling, while inner power planes may use 1 oz or 2 oz copper for current handling. However, thick copper on an internal layer can act as a heat sink during laser drilling, causing inconsistent via depth. To avoid this, designers can use clearance windows in solid copper planes beneath microvias, allowing the laser to stop cleanly on a target pad rather than drilling into a thick plane. This practice also reduces the risk of plating voids and improves microvia reliability in high-current designs.
Layout, Routing, and DFM Strategies for Microvia Reliability
Effective HDI layout begins with the escape routing strategy for fine-pitch components. A 0.5 mm pitch BGA may require laser microvias with 0.1 mm drill diameter and 0.25 mm capture pads, while a 0.4 mm pitch package may need via-in-pad with filled and capped microvias to provide a flat surface for soldering. In these dense areas, the designer must balance via count, routing channels, and impedance control. Using microvias only in the outer rows and through-hole vias further away from the package can reduce cost, but it may limit routing density and require more layers. In many high-speed designs, placing a microvia directly in each BGA pad is better for signal integrity because it eliminates the dog-bone stub and reduces parasitic inductance.
When a microvia is placed in a component pad, it must be copper filled and plated flat to prevent solder from wicking into the hole during assembly. The fill material must match the thermal expansion of the surrounding laminate as closely as possible, otherwise thermal cycling can cause cracks at the via rim. For high-reliability applications such as medical or aerospace electronics, designers should specify flat, void-free copper filling and require microsection inspection on qualification builds. The pad surface finish must also be compatible with fine-pitch assembly, with ENIG or ENEPIG often preferred for flatness and wire bondability.
Signal integrity in HDI design depends heavily on the return path. Every high-speed signal via should have adjacent ground return vias to minimize loop inductance and reduce crosstalk. A ground microvia placed near each signal microvia creates a low-inductance path and helps maintain impedance continuity through the layer transition. This is especially important for differential pairs operating above 5 Gbps, where the via transition can become a major discontinuity. In some cases, the designer must tune the antipad size and pad diameter to match the via impedance to the trace impedance. Simulation tools can model the microvia barrel, pad, and clearance hole to identify resonances or insertion loss problems before fabrication.
Design for manufacturing is not a final checklist; it should guide every placement and routing decision. The panel layout must allow for laser scaling and registration targets, while the board edge should maintain sufficient distance from microvias to prevent breakout during routing or assembly. Via density should be reviewed layer by layer, because too many microvias in a small area can weaken the laminate and create stress concentration. The designer should also minimize the number of unique microvia sizes to simplify laser tooling and inspection. When the design requires a mix of through-hole, blind, buried, and microvia structures, clear documentation and layer-by-layer build notes are essential. By treating the microvia as a precise mechanical feature rather than a simple electrical connection, you create a board that can be manufactured repeatedly at high yield and performs reliably in the field.
A Kazakh software architect relocated to Tallinn, Estonia. Timur blogs in concise bursts—think “micro-essays”—on cyber-security, minimalist travel, and Central Asian folklore. He plays classical guitar and rides a foldable bike through Baltic winds.